Strained Silicon

                                         ....mechanically

    We have reproducibly achieved simultaneous increases in both output and speed by 20% to 30% in n- and p-MOSFETs. Our technique is to apply mechanical stress to commercially available ICs after their IC processing is complete. Wafers are thinned to less than 10 microns (membrane dimensions) and are mounted on a polymer carrier. Here are thinned processed wafers: on clear transparent polymer carrier and on a green flexible polymer carrier.

    Tensile stress is applied in one or more directions and a permanent substrate is bonded to the wafer while it is held under tension.

 Strain is kept within the elastic range and so defects are not an issue. We can bond to most any semiconductor permanent substrate. Here is a SOI, Rad Hard strained wafer on quartz, fabricated by the above method in just one of the many permutations possible. Our technique has been successfully applied to bulk, partially depleted and fully depleted architectures.

Other wafer scale techniques (than ours) are limited to biaxial strain. Process-induced methods become increasingly difficult as at small feature size 'plus' and 'minus' stresses cancel.
 

    Belford Research offers an entirely new way to strain silicon – mechanically. Our new post-processing wafer scale technique has attained unparalleled increases in both output and speed. We have Diverged from standard IC processing we have delved into membrane physics. Our straining technique is inherently versatile and intelligent. It benefits from a matrix of directional-strain data which the technique itself enables.