Active Research

LATEST RESULTS

 

Strained p-MOSFET

This increased output and speed is a result of applying non-compensated uniaxial tensile strain in situ inside the prober. The strain was applied incrementally and the device characterized after each strain increment. Output was taken at a constant gate voltage (1.8 V). The device is a test structure on a commercial IC. Both tensile and compressive strains are used to enhance the p-MOSFET.
 
Our ‘Back-End’ Straining Technology enhances IC device ‘speed and output’ beyond the capabilities of ‘dimension scaling’. Our technology can be applied to any device size. The technology applies tensile stress mechanically to commercially fabricated chips. Our process doubles CMOS output and speed. Optimized, it has the potential to quadruple it. The process is independent of device feature size. It is a macro-process, which has atomic-scale influence and is applicable to every micro-electronic device all the way down to quantum devices. We apply strain after IC fabrication is complete, taking full advantage of all state-of-the-art processing. Ours is an enabling technology, which we have demonstrated to increase bulk silicon's mobility by a factor of two by applying a mere 0.05% uniaxial tensile strain.

Our “Front-End” Straining Technology induces strain during SOI manufacture via differential thermal and dCTE wafer bonding.
Tensile strain increases mobility and decreases the band gap; making strained-silicon essentially a new material. Our Technology has general application ranging from mainstream electronics CMOS to optical devices such as solar cells and photo-diodes.

Our research has featured and been sponsored by a number of National Programs:

SBIR, BMDO 2000-2003

“Next Again Generation Radiation Hard CMOS”

BAA ONR 2000-2001, as part of

“Long Range Scientific and Technology Research in Semiconductor Materials”

SBIR MDA 2002-2003

“Strain-Enhanced Tunnel Diode Technology”

SBIR MDA 2003-2004

“Gallium Nitride Device Technology”

BAA DARPA/MTO 2003-2004

 

“Novel Approach to Ultra-High-Speed, Fully Integrated Bipolar and Unipolar Devices”

NSF 2003-Present

“Ge-Free Strained Silicon Via dTCE Bonding”
CONGRESSIONAL Plus to the SBIR, BMDO 2000-2003 project, giving a Phase III “Next Again Generation Radiation Hard CMOS”


The Present & The Future

We have obtained outstanding results at device level and are now investing our energies to creating tooling for a wafer-level process. We are currently determining the electronic effects of high level straining on a number of CMOS architectures. In the pipeline are four novel uniaxial and three biaxial straining procedures. Our intention is to license our technology to IC manufacturers, Negotiations are currently in progress. We are currently looking to expand our company to include a research base in opto-electronics technology.